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qlus2208-pt280c device data sheet 1 ? ? QLUS2280-PT280C device data sheet utopia level 2 slave bridge 1.0 utopia level 2 (l2) bridge features implements two utopia l2 slaves providing a solution to bridge utopia master devices compliant with atm-forum af-phy-0039.000, june 1995 single phy meets 50mhz performance offering up to 400mbps cell rate transfers single chip solution for im proved system integration support cell level transfer mode cell and clock rate decoup ling with on chip fifos up to 1.5 kbyte of on chip fifo per data direction integrated management interface and built-in errored cell discard atm cell size programmable via external pins from 16 to 128 bytes optional utopia parity generation/che cking enable/disable via external pin built in jtag port (ieee1149 compliant) simulation model available for sy stem level verification (contact quicklogic for details) solution also available as fl exible soft-ip core, delivered with a full device modelization and verification testbenches
2 www.quicklogic.com ? 2001 quicklogic corporation QLUS2280-PT280C device data sheet 2.0 utopia overview the utopia (universal test & operations phy interface for atm) interface is defined by the atm forum to provide a standard inte rface between atm devices and atm phy or sar (segmentation and re-assembly) devices. figure 1: utopia reference model the utopia standard defines a full duplex bus interface with a master/slave paradigm. the slave interface responds to the requests from the master. the master performs phy arbitration and initiates data transf ers to and from the slave device. the atm forum has standardized the utopia le vels 1 (l1) to 3 (l3). each level extends the maximum supported interface speed from oc3, 155mbps (l1) over oc12, 622mbps (l2) to 3.2gbit/s (l3). the following table 1 gives an overview of the main differences in these three levels. utopia level 1 implements an 8-bit interfac e running at up to 25mhz. level 2 adds a 16 bit interface and increases the speed to 50mhz . level 3 extends the interface further by a 32 bit word-size and speeds up to 104mhz pr oviding rates up to 3.2 gbit/s over the interface. in addition to the diffe rences in throughput, utopia level 2 uses a shared bus offering to physically share a single interface bus between one master and up to 31 slave devices (multi-phy or mphy operation). this allows the implementation of aggregation units that table 1: utopia level differences utopia level interface width max. interface speed maximum throughput 1 8-bit 25 mhz 200 mbps (typ. oc3 155 mbps) 2 8-bit, 16-bit 50 mhz 800 mbps (typ. oc12 622 mbps) 3 8-bit, 32-bit 104 mhz 3.2 gbps (typ. oc48 2.5 gbps)
qlus2208-pt280c device data sheet 3 QLUS2280-PT280C device data sheet multiplex several slave devices to a single ma ster device. the level 1 and level 3 are point- to-point only, whereas level 1 has no notion of multiple slaves. level 3 still has the notion of multiple slaves, but they must be implemen ted in a single physical device connected to the utopia interface. 3.0 utopia slave/slave bridge application as it is not possible to connect two master devices together, th e slave/slave bridge provides the necessary interfaces to convey between two master devices as shown in figure 2. figure 2: utopia slave bridge the bridge automatically transfer s data as soon as it becomes available from one side to the other. internal asynchronous fifos enable independent clock domains for each interface.
4 www.quicklogic.com ? 2001 quicklogic corporation QLUS2280-PT280C device data sheet 4.0 application figure 3: slave/slave bridge connecting two master devices data flows from the bridge's tx ports to the corresponding rx ports on the other side of the bridge.
qlus2208-pt280c device data sheet 5 QLUS2280-PT280C device data sheet 5.0 core pinout on the utopia interfaces, the core implements all the required utopia signals and provides all the utopia optional signals (indicated by an 'o' in the following tables). the optional utopia signals are activated during the core configuration and inactive utopia signals should be left unconnected (outpu ts) or tied to a zero logic le vel (inputs) as specified in the following tables. in addition to the utopia interface signals, error indication signals are available for error monitoring or statistics. an e rror indication always shows that a cell has been discarded by the bridge. possible errors are parity or cell-l ength errors on the receive interface of the corresponding utopia interfaces. all utopia interfaces work in the same tran sfer mode (cell level). a mix is not possible. to identify the sides of the core the noti on "west" and "east" for the corresponding interfaces will be used. figure 4: utopia level 3 slave/slave bridge top entity 5.1 signal descriptions table 2: global signal pin mode description reset in active high chip reset
6 www.quicklogic.com ? 2001 quicklogic corporation QLUS2280-PT280C device data sheet note: wtx_.. signals are sampled with west tran smit clock (wtxclk). etx_.. signals are sampled with west receive clock (wrxclk). note: (o) indicates optional signals. table 3: device management interface pin mode description wtx_err out transmit error indication on west interface. when driven high, indicates that an errored cell (wrong parity or wrong length) was received from the device connected to the west interface and is discarded. wtx_err_stat(1:0) out transmit error status information for west interface. when wtx_err is driven, indicates the error status of the discarded cell: ? wtx_err_stat(0) : when set to '1' indica tes that a cell is discarded because of a parity error. wtx_err_stat(1) : when set to '1' indicates that a cell is discarded because it has a wrong length (consecutive assertion of ut_tx_soc on the utopia interface within less than a complete cell time). etx_err out transmit error indication on east interfac e. when driven high, indicates that an errored cell (wrong parity or wrong length) was received from the device connected to the east interface side. etx_err_stat(1:0) out transmit error status information for east receive interface. when etx_err is driven, indicates the error status of the discarded cell: ex_err_stat(0) : when set to '1' indica tes that a cell is discarded because of a parity error. etx_err_stat(1) : when set to '1' indica tes that a cell is discarded because it has a wrong length (consecutive assertion of ut_tx_soc on the utopia interface within less than a complete cell time). table 4: west utopia slave transmit interface pin mode description wtxclk in 50mhz transmit byte clock. the core samples all utopia transmit signals on txclk rising edge. wtxdata[7:0] in transmit data bus. wtxprty in transmit data bus parity. standard odd or non-standard even parity can be optionally checked by the connected slave. when the parity check is disabled during t he core configuration, or not used in the design, the pin txpr ty should be tied to '0'. wtxsoc in transmit start of cell. asserted by the mast er to indicate that the current word is the first word of a cell. wtxenb in active low transmit data transfer enable. wtxclav[0] out cell buffer available. asserted in octet level transfers to indicate to the master that the fifo is almost full (active low) or, in cell level transfers, to indicate to the master that the phy port fifo has space to accept one cell. wtxclav[3:1] (o) out extra fifo full / cell buffer available. in mphy mode and when direct status indication is selected during the core configuration, one txclav signal is implemented per phy port. the maximum number of clav signals is limited to four. wtxaddr[4:0] in utopia transmit address. when the core operates in mphy mode, address bus used during polling and slave port selection. bit 4 is the msb. txaddr(4:0) becomes optional (and should be left open) when the core does not operate in mphy mode.
qlus2208-pt280c device data sheet 7 QLUS2280-PT280C device data sheet note: (o) indicates optional signals. table 5: west utopia slave receive interface pin mode description wrxclk in 50mhz receive byte clock. the core sa mples all utopia rece ive signal s on rxclk rising edge. wrxdata[7:0] out receive data bus. wrxprty (o) out receive data bus parity. standard odd or non standard even parity can be optionally generated by the utopia slave core. when the parity generation is disabled during the core configuration, the pin rxprty can be let unconnected. wrxsoc out receive start of cell. asserted to indicate that the current word is the first word of a cell. wrxenb in active low transmit data transfer enable. wrxclav[0] out cell buffer available. asserted in octet level transfers to indicate to the master that the fifo is almost empty (active low) or, in cell level transfers, to indicate to the master that the phy port fifo has space one cell available in the fifo. wrxclav[3:1] (o) out extra fifo full / cell buffer available. in mphy mode and when direct status indication is selected, one rxclav si gnal is implemented per phy port. the maximum number of clav signals is limited to four. wrxaddr(4:0) in utopia receive address. when the core operates in mphy mode, address bus used during polling and slave port selection. bit 4 is the msb.txaddr(4:0) becomes optional (and should be left open) when the core does not operate in mphy mode. table 6: east utopia slave transmit interface pin mode description etxclk in 50mhz transmit byte clock. the core samples all utopia transmit signals on txclk rising edge. etxdata[7:0] in transmit data bus. etxprty in transmit data bus parity. standard odd or non-standard even parity can be optionally checked by the connected slave. when the parity check is disabled during t he core configuration, or not used in the design, the pin txprty should be left open. etxsoc in transmit start of cell. asserted by the mast er to indicate that the current word is the first word of a cell. etxenb in active low transmit data transfer enable. etxclav[0] out cell buffer available. asserted in octet level transfers to indicate to the master that the fifo is almost full (active low) or, in cell level transfers, to indicate to the master that the phy port fifo has space to accept one cell. etxclav[3:1] (o) out extra fifo full / cell buffer available. in mphy mode and when direct status indication is selected during the core configuration, one txclav signal is implemented per phy port. the maximum number of clav signals is limited to four. etxaddr[4:0] in utopia transmit address. when the core operates in mphy mode, address bus used during polling and slave port select ion. bit 4 is the msb.txaddr(4:0) becomes optional (and should be left open) when the core does not operate in mphy mode.
8 www.quicklogic.com ? 2001 quicklogic corporation QLUS2280-PT280C device data sheet the configuration pins are not intended for change during operation. they are usually board wired to configure the device for operation. table 7: east utopia slave receive interface pin mode description erxclk in 50mhz receive byte clock. the core samples all utopia receive signals on rxclk rising edge. erxdata[7:0] out receive data bus. erxprty (o) out receive data bus parity. standard odd or non standard even parity can be optionally generated by the utopia slave core. when the parity generation is disabled dur ing the core configuration, the pin rxprty can be let unconnected. erxsoc out receive start of cell. asserted to indicate that the current word is the first word of a cell. erxenb in active low transmit data transfer enable. erxclav[0] out cell buffer available. asserted in octet level transfers to indicate to the master that the fifo is almost empty (active low) or, in cell level transfers, to indicate to the master that the phy port fifo has space one cell available in the fifo. rxclav[3:1] (o) out extra fifo full / cell buffer available. in mphy mode and when direct status indication is selected, one rxclav si gnal is implemented per phy port. the maximum number of clav signals is limited to four. erxaddr(4:0) in utopia receive address. when the core operates in mphy mode, address bus used during polling and slave port selection. bit 4 is the msb. taddr(4:0) becomes optional (and should be left open) when the core does not operate in mphy mode. table 8: device configuration pins pin mode description prty_en in enable parity checking on the utopia interface. if disabled (tied to 0), the wrx_err_st at(0) signal can be ignored and left open and the rx parity input should be tied to 0. also the tx parity pins can be left open. cellsize[7:0] in define cellsize: sets the size in bytes of a cell. binary value to be set usually by board wiring.
qlus2208-pt280c device data sheet 9 QLUS2280-PT280C device data sheet 6.0 global signal distribution the externally provided utopia transmit and receive clocks are connected to global resources to provide low skew and fast chip le vel distribution. in both data directions, the two corresponding utopia interfaces are decoupled by asynchronous fifos. therefore each interface runs completely independently each at its own tx and rx clocks which typically are 50 mhz. the error indications of the two receive interfaces are always sampled within the west clock domains. the errors of the east tx (receiving) interface is available on the etx_err signal, which is handled using the west clock domain (wrxclk). the west tx (receiving) error is directly derived from the west tx block (wtxclk). figure 5: slave/slave bridge clock distribution
10 www.quicklogic.com ? 2001 quicklogic corporation QLUS2280-PT280C device data sheet 7.0 functional description ? utopia interface the utopia bridge operates in single phy mode. therefore no a ddress bus and only a single status pin (clav[0]) per direction is used on the interfaces. 7.1 utopia interface sing le phy transmit interface the transmit interface is controlled by the master. the transmit interface has data flowing in the same direction as the atm enable ut_tx_enb . the atm transmit block generates all outp ut signals on the rising edge of the ut_txclk . transmit data is transferred from the master to slave via the following procedure. the slave indicates it can accept data using the ut_txclav signal, then the master drives data onto ut_txdat and asserts ut_txenb . the slave controls the flow of data via the ut_txclav signal. 7.1.1 cell level transfer ? single cell the slave asserts ut_txclav 1 when it is capable of accepting the transfer of a whole cell. the master asserts ut_txenb (low) to indicates that it drives valid data to the slave 2 . together with the first octet of a cell, the master device asserts ut_txsoc for one clock cycle 3 . to ensure that the master does not cause transmit overrun, the slave deasserts ut_txclav at least 4 cycles before the end of a cell if it cannot accept the immediate transfer of the subsequent cell 4 . the master can pause the cell transfer by de-asserting ut_txenb 5 . to complete the transfer to the slave, the master de-asserts ut_tx_enb 6 . figure 6: single cell transfer ? cell level transfer
qlus2208-pt280c device data sheet 11 QLUS2280-PT280C device data sheet 7.1.2 cell level transfer ? back to back cells when, during a cell transfer, the slave is able to receive a subsequent cell, the master can keep ut_txenb asserted between two cells 1 and asserts ut_txsoc , to start a new cell transfer, immediately after the la st octet of the previous cell 2 . figure 7: back to back cell transfer ? cell level transfer 7.2 utopia interface single phy receive interface the receive interface is controlled by the master. the receive interface has data flowing in the opposite direction to the master enable ut_rxenb . receive data is transferred from the slave to master via the following procedure. the slave indicates it has valid data, then the master asserts ut_rxenb to read this data from the slave. the slave indicates valid data (the reby controlling the data flow) via the ut_rxclav signal. 7.2.1 cell level transfer - single cell the slave asserts ut_rx_clav when it is ready to send a complete cell to the master device 1 . the master interface asserts ut_rxenb to start the cell transfer. the slave samples ut_rxenb and starts driving data 2 . the slave asserts ut_rxsoc together with the cell first word to indicate the start of a cell 3 . the master can pause a transfer by de-asserting ut_rxenb 4 . the slave samples high ut_rxenb and stops driving data 5 . to resume the transfer, the master re-asserts ut_rxenb 6 . the slave samples low ut_rxenb and starts driving valid data 7 . the master drives ut_txenb high one before the expected end of the current cell if the slave has no more cell to transfer 8 . the slave de-asserts ut_rxclav to indicate that no new cell is available 9 .
12 www.quicklogic.com ? 2001 quicklogic corporation QLUS2280-PT280C device data sheet figure 8: single cell transfer - cell level transfer 7.2.2 cell level transfer - back to back cells if the master keeps ut_rxenb asserted at the end of a cell transfer 1 and if the slave has a new cell to send, the slave keeps ut_rxclav asserted 2 and immediately drives the new cell asserting ut_rxsoc to indicate the start of a new cell 3 . figure 9: back to back cells transfer - cell level transfer note: if the master keeps ut_rxenb asserted at the end of a packet and if the slave does not have a new cell available, the slave de-asserts ut_rxclav and the data of the bus ut_rxdat are invalid.
qlus2208-pt280c device data sheet 13 QLUS2280-PT280C device data sheet 8.0 core management and error handling on egress, the core is designed to handle and report utopia errors su ch as parity error or wrong cell length. errored cells are discarded with an error status indication provided to the user phy application. when an errored cell is received on the utopia interface, the core discards the complete cell and provides a cell discard indication to the user phy application (signal eg_err(n) asserted) 1 together with a cell discard status (signal eg_err_stat(1:0) ) 2 . note: eg_err is routed to the corresponding wtx_err and etx_err respectively (see figure 4). figure 10: cell discard indication the signals are sampled on the corresponding clocks from the west interface: etx_... sampled with wrxclk (west receive clock) wtx_... sampled with wtxclk (west transmit clock) table 9: error status word bit coding error status bit name description 0 parity_err valid when wtx/etx_err is asserted. if set to one indicates that a cell is discarded wi th a parity error decoded by the core. 1 length_err valid when wtx/etx_err is asserted. if set to one indicates that a cell is discarded with a cell length error detected on the utopia interface.
14 www.quicklogic.com ? 2001 quicklogic corporation QLUS2280-PT280C device data sheet 9.0 complexity and performance summary 9.1 timing parameters definition figure 11: tco timing parameter definition figure 12: tsu timing parameter definition
qlus2208-pt280c device data sheet 15 QLUS2280-PT280C device data sheet note: timing model "worst" case is used. table 10: 8-bit utopia interface timing characteristics parameter typ max unit tco 7.5 6.5 ns tsu 2.5 2.1 ns wrxclk 50 mhz wtxclk 50 mhz erxclk 50 mhz etxclk 50 mhz minimum reset time 50 ns
16 www.quicklogic.com ? 2001 quicklogic corporation QLUS2280-PT280C device data sheet 10.0 device pinout 10.1 signals overview *: active low signal note: unused pins (data busses) in the following tables are to be handled like "nc". table 11: signals overview table signals description wrxclk, wrxclav, wrxenb*,wrxdat, wrxsoc west utopia receive interface wtxclk, wtxclav, wtxenb*, wtxdata, wtxsoc west utopia transmit interface wtx_err, wtx_err_stat west interface error indication (sampled with wtxclk) . erxclk, erxclav, erxenb*, erxdata, erxsoc east utopia receive interface etxclk, etxclav, etxenb*, etxdata, etxsoc east utopia transmit interface etx_err, etx_err_stat east interface er ror indication (sampl ed with wrxclk) prty_en, cellsize configuration pins to be board wired.cellsize [0] should be tied to gnd. reset active high device reset gnd ground vcc device power 2.5 v clk(x) unused clock inputs should be tied to gnd ioctrl(x) vccio(x) io power 3.3 v inref(x) connect to gnd pllrst(x) connect to gnd or vcc pllout(x) connect to gnd or vcc vccpll(x) gndpll(x) tck, trstb jtag signals. connect to gnd tms, tdi jtag signals. connect to vcc tdo jtag signal. leave open iov nc not connected. should be left open
qlus2208-pt280c device data sheet 17 QLUS2280-PT280C device data sheet 10.2 280 pin fpgba (pt280) device diagram figure 13: pt280 bottom view west receive error indication east receive error indication device configuration qlus2280 -pt280c
18 www.quicklogic.com ? 2001 quicklogic corporation QLUS2280-PT280C device data sheet 10.3 280 pin fpbga (pt280) pinout table table 12: 280 pin fpbga (pt280) pinout table pin function pin function pin function pin function pin function a1 pllout(3) d1 n/c g19 n /c n16 n/c u6 inref(a) a2 gndpll(0) d2 n/c h1 n/c n17 n/c u7 n/c a3 etx_err d3 n/c h2 n/c n18 ioctrl(c) u8 n/c a4 etx_err_stat[0] d4 n/c h3 n/c n19 ioctrl(c) u9 vccio(a) a5 etx_err_stat[1] d5 n/c h4 n/c p1 n/c u10 erxclk a6 ioctrl(f) d6 cellsize[0] h5 vcc p2 n/c u11 vccio(b) a7 wtxclav[0] d7 prty_en h15 vcc p3 ioctrl(h) u12 n/c a8 wtxprty d8 reset h16 vcc p4 inref(h) u13 n/c a9 wtxenb d9 clk(8) h17 n/c p5 vcc u14 ioctrl(b) a10 wtxclk d10 wrxclav[0] h18 n/c p15 gnd u15 vccio(b) a11 wtxsoc d11 wrxprty h19 n/c p16 n/c u16 etxdat[5] a12 wtxdat[0] d12 wrxenb j1 n/c p17 n/c u17 tdo a13 wtxdat[1] d13 inref(e) j2 n/c p18 wtx_err u18 pllrst(2) a14 ioctrl(e) d14 wrxsoc j3 vccio(g) p19 wtx_err_stat[0] u19 etxprty a15 wtxdat[2] d15 wrxdat[0] j4 n/c r1 erxdat[7] v1 pllout(2) a16 wtxdat[3] d16 wrxdat[1] j5 gnd r2 n/c v2 gndpll(3) a17 wtxdat[4] d17 wrxdat[2] j15 vcc r3 vccio(h) v3 gnd a18 pllrst(1) d18 wrxdat[3] j16 n/c r4 n/c v4 erxprty a19 gnd d19 wrxdat[4] j17 vccio(d) r5 gnd v5 erxenb b1 pllrst(0) e1 cellsize[3] j18 n/c r6 gnd v6 ioctrl(a) b2 gnd e2 cellsize[2] j19 n/c r7 vcc v7 n/c b3 wtxdat[5] e3 vccio(g) k1 vcc r8 vcc v8 n/c b4 wtxdat[6] e4 cellsize[1] k2 tck r9 gnd v9 n/c b5 wtxdat[7] e5 gnd k3 n/c r10 gnd v10 clk(1) b6 inref(f) e6 vcc k4 n/c r11 vcc v11 clk(4) b7 n/c e7 vcc k5 gnd r12 vcc v12 n/c b8 n/c e8 vcc k15 gnd r13 vcc v13 n/c b9 tms e9 vcc k16 n/c r14 vcc v14 inref(b) b10 clk(6) e10 gnd k17 n/c r15 gnd v15 n/c b11 n/c e11 gnd k18 n/c r16 etxdat[3] v16 etxdat[6] b12 n/c e12 vcc k19 trstb r17 vccio(c) v17 etxdat[1] b13 ioctrl(e) e13 vcc l1 n/c r18 etxenb v18 gndpll(2) b14 n/c e14 gnd l2 n/c r19 wtx_err_stat[1] v19 gnd b15 n/c e15 gnd l3 vccio(h) t1 erxdat[2] w1 gnd b16 n/c e16 wrxdat[5] l4 n/c t2 erxdat[3] w2 pllrst(3) b17 vccpll(1) e17 vccio(d) l5 vcc t3 erxdat[4] w3 nc b18 gndpll(1) e18 inref(d) l15 gnd t4 erxdat[5] w4 nc b19 pllout(0) e19 ioctrl(d) l16 n/c t5 erxdat[6] w5 nc c1 n/c f1 inref(g) l17 vccio(c) t6 ioctrl(a) w6 erxclav[0] c2 vccpll(0) f2 ioctrl(g) l18 n/c t7 n/c w7 n/c c3 n/c f3 cellsize[5] l19 n/c t8 n/c w8 n/c c4 n/c f4 cellsize[4] m1 n/c t9 n/c w9 tdi c5 vccio(f) f5 gnd m2 n/c t10 n/c w10 etxclk c6 ioctrl(f) f15 vcc m3 n/c t11 clk(3) w11 n/c c7 n/c f16 ioctrl(d) m4 n/c t12 n/c w12 n/c c8 n/c f17 wrxdat[6] m5 vcc t13 n/c w13 n/c c9 vccio(f) f18 wrxdat[7] m15 vcc t14 n/c w14 ioctrl(b) c10 wrxclk f19 n/c m16 inref(c) t15 n/c w15 etxdat[10] c11 vccio(e) g1 n/c m17 n/c t16 etxdat[4] w16 etxdat[7] c12 n/c g2 cellsize[7] m18 n/c t17 vccpll(2) w17 etxdat[2] c13 n/c g3 ioctrl(g) m19 n/c t18 etxsoc w18 etxdat[0] c14 n/c g4 cellsize[6] n1 ioctrl(h) t19 etxclav[0] w19 pllout(1) c15 vccio(e) g5 vcc n2 n/c u1 erxsoc c16 n/c g15 vcc n3 n/c u2 erxdat[0] c17 n/c g16 n/c n4 n/c u3 vccpll(3) c18 n/c g17 n/c n5 vcc u4 erxdat[1] c19 n/c g18 n/c n15 vcc u5 vccio(a)
qlus2208-pt280c device data sheet 19 QLUS2280-PT280C device data sheet 11.0 references atm forum, utopia level 2, af-phy-0039.000 12.0 contact quicklogic corp. tel : 408 990 4000 (us) : + 44 1932 57 9011 (europe) : + 49 89 930 86 170 (germany) : + 852 8106 9091 (asia) : + 81 45 470 5525 (japan) e-mail : info@quicklogic.com internet : www.quicklogic.com
20 www.quicklogic.com ? 2001 quicklogic corporation QLUS2280-PT280C device data sheet

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